Conventionally, a clock-data recovery (“CDR”) circuit, such as of a multi-gigabit serial data transceiver for example, may align a data clock to a median position with respect to corresponding edges of a waveform data eye, generally after equalization. Transmitted information may include data represented by symbols. Symbols may be sampled after this median position is aligned to a data clock, such as at one-half of a bit period for example. Such sampling position or sampling phase, namely at an interpolated phase sampling point, may be less than desirable due to an asymmetric data eye and/or a sampling phase position that is not one-half of a period T (i.e., 180 degrees) of a data eye away from a corresponding data crossing (“dXd”). A data eye may be asymmetric for any of several reasons, including without limitation precursor inter-symbol interference (“ISP”).
However, for purposes of clarity by way of example without loss of generality, a CDR makes use of data eye and crossing information to determine a sampling phase in a middle region or median of a data eye and a corresponding edge to use for purposes of locking. A sampling phase to lock to the middle region of a data eye for a symbol may use a data slicer clock, and a corresponding crossing slicer clock is generally used for an associated edge of such a data eye. A CDR circuit is generally locked to such a median-based sampling phase.
For some CDR circuits, including bang-bang CDR circuits, a metastable state may arise. Because of this metastable state, it may take such CDR circuits more time to lock. However, for burst modes, and other high-speed serial signaling modes, such additional time to lock may negatively impact performance.